Analyzing path delays for accelerated testing of logic chips
Emily Ray, Barry P. Linder, et al.
IRPS 2015
Near-threshold computing and scaling are combined to operate SRAMs in regions where they are close to being unstable. One consequence of this is an increase in single event upsets (SEUs), due to the minimal charge stored on nodes during reduced voltage operation. In this paper, both modeling and measurements [with heavy ions, MeV and low energy protons (LEPs)] are reported for a 32-nm silicon on insulator SRAM, over a range of 0.4-1.05 V. The results show that the SEU rate increases by 3X at low-supply voltages, where very LEPs are able to upset these devices. This can be a reliability concern when running SRAMs at near-threshold voltages in LEP space environments.
Emily Ray, Barry P. Linder, et al.
IRPS 2015
Jaap Kautz, M. Copel, et al.
Physical Review B - CMMP
Ethan H. Cannon, Daniel D. Reinhardt, et al.
IRPS 2004
David F. Heidel, Kenneth P. Rodbell, et al.
IBM J. Res. Dev