Shu-Jen Han, Alberto Valdes-Garcia, et al.
IEDM 2011
The time delay of digital signals propagating through CMOS gates is unavoidably subject to some timing jitter, which imposes a lower limit on circuit jitter performance. Some of the jitter is fundamental to the nature of CMOS gates, and cannot be eliminated, and some is due to power supply noise, which can be controlled to some extent. A technique for distinguishing between these two components, and obtaining their numerical values, is described, and the technique is demonstrated with simple inverters.
Shu-Jen Han, Alberto Valdes-Garcia, et al.
IEDM 2011
Jean-Olivier Plouchart, Noah Zamdmer, et al.
IBM J. Res. Dev
Mark B. Ketchen, Manjul Bhushan, et al.
IEEE International SOI Conference 2005
Joachim N. Burghartz, Jean-Olivier Plouchart, et al.
IEEE Electron Device Letters