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Publication
DRC 2001
Conference paper
Low-power CMOS at Vdd=4kT/q
Abstract
The operation of complimentary metal oxide semiconductor (CMOS) power-delay product at subthreshold voltages was demonstrated. Experimental results showed that capacitive loading was due to junction, wire and gate fringe capacitances. This was due to smaller gate-to-inversion layer capacitance as compared to the operation above the threshold voltage.