VLSI Technology 1989
Conference paper

Submicron high performance bipolar technology


An optimized sub-micron double-poly self-aligned bipolar technology has been developed in conjunction with a low-temperature, beakless field isolation. The integrated process presented yields a structure with nominal topography, a well-designed base-collector profile, a sub-100-nm base width, and reduced parasitic capacitances. Conventional ECL (emitter coupled logic) circuits with 35-ps gate delays, a novel AC-coupled active-pull-down (APD) ECL circuit with 21-ps gate delay, and a 1/128 static frequency divider operated at a maximum clocking frequency of 12.5 GHz have been demonstrated using this technology.