A software-assisted peak current regulation scheme to improve power-limited inference performance in a 5nm AI SoC
- Monodeep Kar
- Joel Silberman
- et al.
- 2024
- ISSCC 2024
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45 results for Zhibin Ren
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling
- Ankur Agrawal
- Saekyu Lee
- et al.
- 2021
- ISSCC 2021
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Statistical measurement of random telegraph noise and its impact in scaled-down high-κ/metal-gate MOSFETs
- H. Miki
- N. Tega
- et al.
- 2012
- IEDM 2012
Assessment of fully-depleted planar CMOS for low power complex circuit operation
- Zhibin Ren
- S. Mehta
- et al.
- 2011
- IEDM 2011
Hysteretic drain-current behavior due to random telegraph noise in scaled-down FETs with high-κ/metal-gate stacks
- Hiroshi Miki
- Naoki Tega
- et al.
- 2010
- IEDM 2010
Reduction of random telegraph noise in high-κ / metal-gate stacks for 22 nm generation FETs
- N. Tega
- H. Miki
- et al.
- 2009
- IEDM 2009
High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor
- B. Yang
- R. Takalkar
- et al.
- 2008
- IEDM 2008
Direct silicon bonded (DSB) substrate solid phase epitaxy (SPE) integration scheme study for high performance bulk CMOS
- Haizhou Yin
- C.Y. Sung
- et al.
- 2006
- IEDM 2006
High performance CMOS bulk technology using direct silicon bond (DSB) mixed crystal orientation substrates
- Chun-Yung Sung
- Haizhou Yin
- et al.
- 2005
- IEDM 2005