Impact of Line and Via Resistance on Device Performance at the 5nm Gate All Around Node and beyond

Abstract

The impact of back-end-of-line (BEOL) loading on logic performance at the 7nm, 5nm and 3nm technology nodes is evaluated using a combination of ab initio, finite-element and circuit analysis methods. The effects of processing variations, including line-edge-roughness (LER) and line height variation (LHV) on line resistance and overall frequency performance are quantified at each technology node. We find that barrier material optimization beyond the 5nm node can reduce via resistance by as much as 26%, resulting in a 2 % performance uplift. Depending on amplitude, the combined effects of LER and LHV can result in a >25% line resistance penalty beyond the 5nm node and a corresponding 8% performance penalty.