Dzung Phan, Vinicius Lima
INFORMS 2023
The NorthPole Architecture achieves high performance with high efficiency by using local memory within a parallel, distributed core array, linked by networks-on-chip to ensure data availability, orchestrated by prescheduled, distributed local control. A 12nm NorthPole Inference Chip (22B transistors, 795mm2) includes a 256-Core Array with 192MB of distributed SRAM. At nominal 400MHz frequency, it computes TOPS exceeding 200 at 8b-, 400 at 4b-, and 800 at 2b-precision with very high utilization.
Dzung Phan, Vinicius Lima
INFORMS 2023
Jehanzeb Mirza, Leonid Karlinsky, et al.
NeurIPS 2023
Hagen Soltau, Lidia Mangu, et al.
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JPDC