High-Speed Low-Power ACCoupled Complementary Push-Pull ECL Circuit

Abstract

This paper presents a high-speed low-power accoupled complementary push-pull ECL (AC-PP-ECL) circuit. The circuit utilizes two capacitors to couple a transient voltage pulse from the common-emitter node of the switching transistors to the bases of a pair of complementary p-n-p/n-p-n push-pull transistors to provide a large transient current during switching. In addition to a reduction of the power consumption and improvement in the pull-up and pull-down capability of the output stage, the circuit scheme completely decouples the collector load resistor R<inf>c</inf>from the delay path, thus allowing a very small switching current to be used for the logic (current switch) stage without degrading the performance. Based on a 0.8-μm double-poly self-aligned complementary bipolar process at a power consumption of 0.5 mW/ gate, the circuit offers 2.1 x improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed. © 1992 IEEE