High performance MTCMOS technique for leakage reduction in hybrid SOI-epitaxial technologies with enhanced-mobility PFET header

Abstract

Power management has become a key constraint in the design of modern digital VLSI chips. Moreover, with minimum transistor dimensions reaching 100-nm and below, traditional scaling has slowed down. The ITRS roadmap has indicated that device mobility enhancement would be necessary to maintain the generational performance improvement in the sub-100nm VLSI era. This paper presents a comprehensive analysis of the popular low-leakage power MTCMOS circuit technique in various emerging technologies with enhanced-mobility PFETs. © 2006 IEEE.