The thermal resistance of a three-dimensional (3D) chip stack has been experimentally clarified by authors [1-6] and an additional cooling solution is strongly required to achieve various structures of 3D chip stacks. Especially, when a high heat dissipating chip is located as a bottom chip, cooling from the bottom side of chips (in other words, from the laminate (substrate) side) is identified to be very effective by authors . For cooling from the bottom side of a laminate, reduction of the thermal resistance of a laminate is important, and the effect of high thermal conductivity insulator (dielectric) is simulated as a function of the thermal via density, and via-hole-fabrication capability in various maker's high thermal conductivity insulator is also discussed. Secondly, placing a graphite sheet in the joint (interconnection) layer between a bottom chip and a laminate is proposed. When a graphite sheet is directly connected to a lid (heat spreader), it is examined how much additional heat density is managed by this cooling structure. As another aspect, in order to effectively conduct the hot spot heat of a bottom chip to large area of a laminate and accommodate various thermal via locations, it is simulated how effectively the hot spot heat of a bottom chip is spread by placing a graphite sheet in the joint layer between a bottom chip and a laminate. For cooling from the bottom side of chips, it is essential to consider the trade-off among thermal, electrical and mechanical performance and it is also discussed.