Dopant-segregation technique for leakage reduction and performance improvement in trigate transistors without raised source/drain epitaxy

A dopant-segregation technique for junction engineering has been demonstrated on trigate transistors using a process flow that does not include raised source/drain epitaxy. It is shown that the dopant-segregation technique reduces the off-state leakage current and improves the on-state performance for NFET devices when compared with control devices built using conventional junction engineering. The dopant-segregation process has no observable impact on PFET device performance. © 1980-2012 IEEE.