Dynamic Guard-Band Features of the IBM zNext System
Tobias Webel, Phillip Restle, et al.
ISSCC 2025
The drive to deliver increasingly powerful and feature-rich integrated circuits has made technology node scaling—the process of reducing transistor dimensions and increasing their density in microchips—a key challenge in the microelectronics industry. Historically, advances in optical lithography patterning have played a central role in allowing this trend to continue. Directed self-assembly of block copolymers is a promising alternative patterning technique that offers sub-lithographic resolution and reduced process complexity. However, the feasibility of applying this approach to the fabrication of critical device layers in future technology nodes has never been verified. Here we compare the use of directed self-assembly and conventional patterning methods in the fabrication of 7 nanometre node FinFETs, using an industrially relevant and high-volume manufacturing-compliant test vehicle. Electrical validation shows comparable device performance, suggesting that directed self-assembly could offer a simplified patterning technique for future semiconductor technology.
Tobias Webel, Phillip Restle, et al.
ISSCC 2025
Apoorve Mohan, Robert Walkup, et al.
ASPLOS 2025
Pooja Aggarwal, Ajay Gupta, et al.
ICSOC 2020
Luciana Meli, Indira Seshadri, et al.
SPIE Advanced Lithography + Patterning 2025