Device Design Considerations for Ultra-Thin SOI MOSFETs

Abstract

The ultra-thin SOI (UTSOI) device is an attractive choice for sub-10nm gate-length scaling. In this work the major issues for UTSOI are addressed. External resistance is minimized by using the Raised Extension (REX) process flow which features an offset spacer to minimize the region of UTSOI outside the channel. The REX process scheme is used to demonstrate improved pFET performance and also to demonstrate the first planar single gate nFET with 8nm gate-length. High temperature mobility measurements show that the channel thickness can be scaled further than previously predicted. UTSOI devices with tungsten gates and HfO 2 gate dielectrics having appropriate threshold voltages are presented for the first time.