Delayed-Staging Hierarchy Optimization

A geometric programming model is developed to optimize delayed-staging (DS) storage hierarchies. These hierarchies have direct paths between the CPU and the k fastest storage levels (k = 1 in a linear hierarchy), allowing for some concurrency in the flow of data through the hierarchy. The criterion for optimization is the minimization of average hierarchy access time subject to budgetary limitations, given the cache access time and the backing-store capacity. The model is fully derived for the k = 2 case, the results are compared to those for equivalent linear hierarchies, and examples are given which illustrate the model's application. From the results we see that optimal hierarchy access time in DS hierarchies is slightly better than for their linear counterparts. Also, we notice that cache sizes are smaller (and cheaper) in the DS case, without requiring significantly larger or faster lower storage levels. Copyright © 1983 by The Institute of Electrical and Electronics Engineers, Inc.