A backtracing-oriented procedure for the analysis of combinational gate-level designs

Abstract

We present an approach to the analysis of combinational gate-level designs, which produces information conducive to the acceleration of the backtracing process, pervasive in automatic test pattern generation algorithms. This analysis yields information which can be used to make intelligent decisions within the search space spanned by the backtracing process. A procedure which embodies this approach is presented, together with experimental results. © 1994.