Copper dual damascene wiring for sub-0.25 μm CMOS technology

Abstract

Recently, IBM announced the implementation of a full copper interconnect scheme which will be manufactured on its high-performance 0.20 μm CMOS products later this year. Features of this technology are presented here, as well as functional verification on CMOS chips. To reach this level, extensive yield, reliability, and stress testing had to be done on test and product-like chips, including those packaged into product modules. Data is presented from this testing, ranging from experiments designed to promote copper contamination of the MOS devices, to functional stressing of packaged SRAM modules. A fully-functional high-performance microprocessor with 6 levels of Cu wiring has also been demonstrated. The results in all areas are equal to or better than standards set by our current Al(Cu) wiring technology. This work demonstrates that the potential problems associated with copper wiring can be overcome to produce reliable and properly-functioning ULSI CMOS chips with a cost-effective, extendible process.