About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
Physical Review Letters
Paper
Conductance in restricted-dimensionality accumulation layers
Abstract
Conductance has been studied in metal-oxide-silicon field-effect transistor accumulation-layer samples in which it is possible to constrict the channel to small dimensions both perpendicular to the surface and perpendicular to the channel. A temperature-dependent conductance σ=σ0exp[-(T0T)n] is observed, where n=12 for small channel widths and n=13 for larger channel widths. It is believed that this behavior arises from a transition from one-dimensional to two-dimensional variable-range hopping in the sample. © 1982 The American Physical Society.