The tunnel FET (TFET) is considered as one of the most promising devices for ultra-low power operation, and it is clear that heterojunction devices are required to achieve simultaneously steep slope and high on-current (Ion). However, technologically, heterojunction TFETs are much more complex than a silicon MOSFET. Our focus has been on dense monolithic integration of complementary III-V heterojunction TFETs on silicon, which may eventually evolve into a hybrid technology platform. In this paper we will give a general overview of the development of TFETs, discuss the challenges and opportunities both at the individual device level as well as in terms of technology development. In particular we will focus on the role of defects on device performance.