Publication
ECTC 2018
Conference paper

Column Interconnects: A Path Forward for Embedded Cooling of High Power 3D Chip Stacks

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Abstract

In this paper we present a novel approach to addressing the challenges of integrating embedded cooling into 3D chip stacks with multiple large high power die layers. 3D chip stacks require the integration of through silicon vias (TSVs) in the active device die layers, with demonstrated reliable production capable processes limiting the height of such vias (and thus the active device die thickness) to approximately 50 micrometers for integrated copper vias, creating constraints on channel height. Limited channel height capability constrains the power which can be transferred to the coolant at reasonable coolant pressure drops. An ideal solution to integrating embedded cooling into a stack of large high power dies would allow higher channel height and require no additional processing of the active dies. In this work we describe and provide initial experimental results for an approach that meets this ideal. In this approach a separate interconnect/channel defining structure is created utilizing a die thinned to a thickness compatible with TSV processes that do not require active device integration. Reliable TSV heights of 100 micrometers or more are obtainable when integration with fine wiring or active devices is not required on either end of the TSV. The thinned die is attached to a handler wafer utilizing a blanket adhesive process. TSV structures along with endpoint metallurgies (pads, solder bumps, etc) are created in the thinned die either before or after thinning and handler attach, depending on the exact TSV and endpoint metallurgy processes chosen. Pillar and/or channel wall structures are lithographically laid out to incorporate the TSVs. The die area outside these pillar/wall structures is completely etched away with a Deep Reactive Ion Etch (RIE) process, leaving an array of fully separated pillar/wall structures attached to the handler wafer. This wafer may, if desired, then be diced into active-die sized arrays. These structures are now attached to receiving pads/solder bumps on one active die or wafer. The handler wafer/die is then released from the structures, leaving them standing attached to the active die or wafer. Finally a second active die or wafer is attached to the other end of the structures, creating coolant channels with embedded TSVs. The process can be repeated with an arbitrary number of active die/interconnect array pairs. The initial experimental work presented here demonstrates this process without integrated TSV's, showing that it is possible to create such structures, attach them to a die, release the handler, and attach a die to the other end of the structures thus creating coolant channels or cavities. This approach and initial demonstration show the potential for reliable high power 3D integration of embedded cooling using active dies incorporating demonstrated TSV processes.

Date

07 Aug 2018

Publication

ECTC 2018

Authors

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