Circuit styles and strategies for CMOS VLSI design on SOI

This paper reviews specific circuit styles and strategies employed in the design of CMOS VLSI on partially-depleted (PD) SOI. These strategies address issues and problems that arise on PD SOI circuits (mainly due to the floating-body effect) such as delay hysteresis, noise margin reduction, etc. These circuit approaches also try to utilize SOI-specific properties to achieve a larger performance gain than that of a simple re-map of a bulk design to SOI. Although many aspects of CMOS design pertaining to SOI will be covered, the emphasis will be on dynamic and static circuits and high-performance SRAM's.