Hiroshi Ito, Reinhold Schwalm
JES
This paper discusses the electrostatic discharge (ESD) robustness in silicon-on-insulator (SOI) high-pin-count high-performance semiconductor chips. The ESD results demonstrate that sufficient ESD protection levels are achievable in SOI microprocessors using lateral ESD SOI polysilicon-bound gated diodes without the need for additional masking steps, process implants or ESD design area. © 2000 Elsevier Science B.V.
Hiroshi Ito, Reinhold Schwalm
JES
U. Wieser, U. Kunze, et al.
Physica E: Low-Dimensional Systems and Nanostructures
Douglass S. Kalika, David W. Giles, et al.
Journal of Rheology
Arvind Kumar, Jeffrey J. Welser, et al.
MRS Spring 2000