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Publication
Journal of Electrostatics
Paper
Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) CMOS technology with aluminum and copper interconnects in advanced microprocessor semiconductor chips
Abstract
This paper discusses the electrostatic discharge (ESD) robustness in silicon-on-insulator (SOI) high-pin-count high-performance semiconductor chips. The ESD results demonstrate that sufficient ESD protection levels are achievable in SOI microprocessors using lateral ESD SOI polysilicon-bound gated diodes without the need for additional masking steps, process implants or ESD design area. © 2000 Elsevier Science B.V.