M.A. Lutz, R.M. Feenstra, et al.
Surface Science
This paper discusses the electrostatic discharge (ESD) robustness in silicon-on-insulator (SOI) high-pin-count high-performance semiconductor chips. The ESD results demonstrate that sufficient ESD protection levels are achievable in SOI microprocessors using lateral ESD SOI polysilicon-bound gated diodes without the need for additional masking steps, process implants or ESD design area. © 2000 Elsevier Science B.V.
M.A. Lutz, R.M. Feenstra, et al.
Surface Science
J.C. Marinace
JES
Arvind Kumar, Jeffrey J. Welser, et al.
MRS Spring 2000
A. Gupta, R. Gross, et al.
SPIE Advances in Semiconductors and Superconductors 1990