Publication
IEEE JSSC
Paper

An Experimental Multiplier Circuit Based on Superconducting Josephson Devices

View publication

Abstract

This paper describes the design, testing, and operation of a 4-bit multiplier circuit based on Josephson tunneling logic (JTL) gates. The algorithm adopted was that of a simple serial 4-bit multiplier consisting of a 4-bit adder with ripple carry, together with a four phase, 8-bit accumulator shift register. The circuit, fabricated using a 25-μm minimum linewidth technology, operated with a minimum cycle time of 6.67 ns (a limit imposed by the external test equipment) giving a 4-bit multiplication time of 27 ns with an average power dissipation of 35 μW per logic gate. With better external pulse generators, or internal Josephson junction generators, the present circuit has been simulated to operate with a 3.0-ns cycle giving a 4-bit multiplication time of 12 ns. Copyright © 1975 by The Institute of Electrical and Electronics Engineers, Inc.

Date

01 Jan 1975

Publication

IEEE JSSC

Authors

Share