Sub-100 ps Experimental Josephson Interferometer Logic Gates

Abstract

Josephson interferometer logic gates have been operated experimentally with an average logic delay of 55 ps per stage. The gates operated with an ac power supply in a latching mode with a reset capabitity consistent with a machine cycle time less than 5 ns, OR, AND, and INVERT functions and fanout capability were demonstrated. Dissipation per gate was about 2.0 µW. Copyright © 1978 by The Institute of Electrical and Electronics Engineers, Inc.