Publication
IEEE T-ED
Paper

A Self-Aligned 1-μm-Channel CMOS Technology with Retrograde n-Well and Thin Epitaxy

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Abstract

A six-mask 1-μm CMOS process with many self-aligned features is described. It uses a thin p-type epitaxial layer on a p+ substrate and a retrograde n-well. Self-aligned TiSi2 is formed on n+ and p+ diffusions to reduce the sheet resistance and to make butted source contacts. It is shown that n+ poly-gated p-channel devices can be properly designed with low threshold magnitudes and good turn-off characteristics. With a 5-V supply, the minimum gate delay of unloaded CMOS ring oscillators is 150 ps/stage. Furthermore, it is demonstrated that this CMOS technology is latchup free since the holding voltage for latchup is higher than 5 V. Copyright © 1985 by The Institute of Electrical and Electronics Engineers, Inc.

Date

01 Jan 1985

Publication

IEEE T-ED