Yuan Taur, D.S. Zicherman, et al.
IEEE Electron Device Letters
Fully scaled NMOS devices, circuits, and dynamic memory with 1/2-µm nominal minimum dimensions at each level have been fabricated using direct-write e-beam patterning. This high-density NMOS technology yields nominally loaded average gate delays of 650 ps/stage with a power dissipation of 38 µW. The characteristics of this technology are presented with specific emphasis placed on features of the design which are unique to submicrometer MOSFET's, including a study of nonscaling effects and their impact on the device and circuit design. Copyright © 1985 by The Institute of Electrical and Electronics Engineers, Inc.
Yuan Taur, D.S. Zicherman, et al.
IEEE Electron Device Letters
Hu H. Chao, Robert H. Dennard, et al.
IEEE Journal of Solid-State Circuits
Jack Y.-C. Sun, Matthew R. Wordeman, et al.
IEEE T-ED
Toshiaki Kirihata, Yohji Watanabe, et al.
IEEE Journal of Solid-State Circuits