Koushik K. Das, Rajiv V. Joshi, et al.
ESSCIRC 2003
Negative Bias Temperature Instability (NBTI) has become an important cause of degradation in scaled PMOS devices, affecting power, performance, yield and reliability of circuits. This paper proposes a scheme to detect PMOS threshold voltage (VTH) degradation using on-chip slew-rate monitor circuitry. The degradation in the PMOS threshold voltage is determined with high resolution by sensing the change in rise time in a stressed ring oscillator. Simulations in IBM's 65nm PD/SOI CMOS technology demonstrate good linearity and an output sensitivity of 0.25mV/mV using the proposed scheme. ©2009 IEEE.
Koushik K. Das, Rajiv V. Joshi, et al.
ESSCIRC 2003
Jae-Joon Kim, Barry P. Linder, et al.
IRPS 2011
Rahul M. Rao, Jeffrey L. Burns, et al.
VLSID/Embedded 2004
Koushik K. Das, Rajiv V. Joshi, et al.
ISLPED 2003