RFIC 2017
Conference paper

A fully-integrated 94-GHz 32-element phased-array receiver in SiGe BiCMOS

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A 94GHz phased array receiver IC in 130nm BiCMOS technology is reported. The design integrates 32 front ends with gain and phase control configurable using look-up table memory, two separate 16:1 power combiner trees, two 94GHz to ∼10GHz (IF) down conversion mixers, an IF to baseband (BB) quadrature down conversion mixer, and a 42GHz PLL followed by a frequency doubler implementing the LO source. The IC occupies an area of 6.7mm×5.6mm and can either support a 32-element phased array or a 16-element polarimetric phased array if connected to 16 dual-polarized antennas. In on-wafer measurements at 94GHz and 25C, the design achieves maximum RF to IF array conversion gain of 39dB, maximum RF to BB array conversion gain of 69dB, 20dB of RF front-end gain programmability, NF of 6 dB, and RMS phase error <1.5° for a 5° phase step. Total power consumption varies from 3W to 4.6W from minimum to maximum RF front-end gain settings.