A compact low-power 3D I/O in 45nm CMOS

Abstract

Three-dimensional (3D) silicon integration technology, featuring thinned die-to-die bonding and through-silicon-via (TSV) interconnections, enables dense local chip-to-chip interconnect [1]. With potentially thousands of multi-Gb/s I/O, support for tens of Tb/s data bandwidth between local chips can be enabled by 3D integration technology, but this ultra-high bandwidth will only be achieved if area and power efficiency challenges for 3D I/O are met. Because 3D interconnect offers reduced loading and hence improved signal integrity as compared to traditional inter-chip channels, 3D cross-chip I/O does not require complex, power-hungry equalization schemes. Reduced swing approaches offer a path to further power reduction for 3D I/O, but the receivers for low-swing schemes are typically complex and consume large area and power [2-3]. This paper addresses this problem, presenting a compact, low-power 3D cross-chip I/O composed of a low-swing Tx and a gated-diode sense-amplifier-based Rx. © 2012 IEEE.