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Publication
CSICS 2005
Conference paper
A low power 10 Gb/s serial link transmitter in 90-nm CMOS
Abstract
A 10Gb/s half-rate serial link differential transmitter is optimized for low power and features a 4:1 multiplexer and a 4-tap feed-forward equalizer. The chip is error-free at 10Gb/s (2 31-1 PRBS) and 125°C, driving an AC-coupled 100 Ohm differential load with a 0.9V peak-to-peak differential (ppd) signal and consuming a total of 174mW (80mA from a 1.65V supply in the output driver section and 35mA from 1.2V in the multiplexer section). © 2005 IEEE.