High-performance, flexible clock synthesis is a key challenge in multiple applications, from high-data-rate I/O to reconfigurable radio and radar. Conventional wireline and wireless LC-VCO based PLLs can cover a large tuning range using multiple frequency bands [1, 2], typically using a calibration loop to select an operating band for the VCO, then allowing the PLL to lock within that band. In effect, the in-band frequency tuning range of a typical high-performance LC-VCO covers a small fraction of the total range, the remainder of which is covered using switched high-Q fixed capacitors. This approach has been favored first due to the typically inferior quality factor of analog varactors as compared to that of high-Q vertical natural capacitors (VNCs) with CMOS switches, and second due to the unacceptable noise sensitivity of the VCO control node if the tuning range is covered using a single high-gain varactor. This traditional banding strategy leads to a number of practical problems. First, the entire VCO frequency range cannot be traversed while maintaining glitch-free phase lock, as changing bands involves simultaneously switching in and out large capacitors. Further, the per-band tuning range must be wide enough to guarantee that mismatch between digitally switched capacitor banks does not result in holes in the frequency transfer curve of the VCO. Finally, sufficient tuning range to accommodate temperature-and supply variation-induced drift must be present within each selected band, placing stringent demands on adjacent band overlap and on band selection algorithms. While one component of eliminating coarse bands, stitching of tuning controls across discrete varactors, has been demonstrated in , the stitching was achieved over only a fraction of the total range of the oscillator.