Publication
RFIC 2011
Conference paper

A 2.4GHz 2Mb/s digital PLL-based transmitter for 802.15.4 in 130nm CMOS

View publication

Abstract

A fully integrated 2.4GHz transmitter for 802.15.4 based on a digital ΣΔ fractional-N PLL is presented. A self-calibrated two-point modulation scheme enables modulation rates much larger than the loop bandwidth. An oversampled 1-bit quantizer is used as a phase detector, reducing spurs and nonlinearity associated with some TDC-based digital PLLs. The prototype achieves an MSK modulation rate of 2Mb/s, delivers -2dBm of output power, and is free of in-band fractional spurs. The transmitter, implemented in 130nm CMOS, consumes 17mW from a 1.2V supply and occupies an active area of 0.6mm2. © 2011 IEEE.

Date

01 Aug 2011

Publication

RFIC 2011

Authors

Share