Publication
A-SSCC 2012
Conference paper

A 5.8GHz digital arbitrary phase-setting Type II PLL in 65nm CMOS with 2.25° Resolution

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Abstract

A fully-integrated 5.8GHz PLL modulator implemented in 65nm CMOS achieves digitally-controlled arbitrary phase generation. The PLL consists of a Type II fractional-N PLL with a 1-bit TDC as its PFD. Digital phase setting, which operates by adding a proportional signal to the PFD output, is incorporated in the PLL. The prototype achieves an average phase resolution of 2.25° and a phase range of more than 720°. The entire PLL and output buffer consumes 11mW. © 2012 IEEE.

Date

01 Dec 2012

Publication

A-SSCC 2012

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