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RFIC 2011
Conference paper

Analytical model for RF power performance of deeply scaled CMOS devices

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Abstract

This paper presents a first order model for RF power of deeply scaled CMOS. The model highlights the role of device on-resistance in determining the maximum RF power. We show excellent agreement between the model and the measured data on 45 nm CMOS devices across a wide range of device widths, under both maximum output power and maximum PAE conditions. The model allows circuit designers to quickly estimate the power and efficiency of a device layout without need for complicated compact models or simulations. © 2011 IEEE.

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RFIC 2011

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