A 2-GHz direct sampling delta-sigma tunable receiver with 40-GHz sampling clock and on-chip PLL

Abstract

This paper presents a 2-GHz tunable direct sampling AL receiver with 40-GHz sampling clock and on-chip PLL, fabricated in a production 130-nm SiGe BiCMOS process. The measured SFDR and SNDR are 59 dB and 59.84 dB, respectively, over a bandwidth of 60 MHz, and the effective number of bits (ENOB) equals 9.65. Compared to the case where an external low-noise 40-GHz clock was used, no SNDR degradation was observed when the on-chip VCO and PLL were employed. The entire receiver with PLL occupies an area of 1.58×2.39 mm2 and consumes 2.19 W when, powered from a 2.5-V supply.