A 1.3 GSample/s 10-tap full-rate variable latency self-timed FIR filter with clocked interfaces

Abstract

A 1.3 GSample/s 10-tap full-rate variable latency self-timed FIR filter with clocked interfaces was presented. The 0.45 mm2 circuit in 0.18 μm complementary metal oxide semiconductor (CMOS) was operational from 1.2 V to 2.1 V power supply. The architecture had 80 mW dissipation at 300 MSample/s, 4 cycles of latency and 500 mW at 1.3 GSample/s and 7 cycles of latency.