A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
Sergey V. Rylov, Troy Beukema, et al.
ISSCC 2016
This article describes a 128-Gb/s pulse amplitude-modulation 4-level (PAM-4) transmitter (TX) implemented in a 14-nm CMOS FinFET technology. Equalization is provided by a fully reconfigurable 3-tap baud-spaced feed-forward equalizer (FFE). The TX uses a segmented tailless current mode logic (CML) driver topology. The key architectural and circuit techniques include the thermometer-encoded driver slices, the clock phase selection circuits to perform segment reassignment to different FFE taps, and coarse-fine tuning of the FFE tap weights. The measured energy efficiencies for PAM-4 signaling are 1.33 pJ/b at 128 Gb/s with 1-Vppd output amplitude and 1.0 pJ/b at 112 Gb/s with 0.6-Vppd output amplitude. These results represent the highest data rate and best energy efficiencies reported to date.
Sergey V. Rylov, Troy Beukema, et al.
ISSCC 2016
A. Serdar Yonar, Pier Andrea Francese, et al.
VLSI Technology and Circuits 2022
John F. Bulzacchelli, Hae-Seung Lee, et al.
IEEE TAS
Timothy O. Dickson, Yong Liu, et al.
IEEE JSSC