S. Cohen, J.C. Liu, et al.
MRS Spring Meeting 1999
As the semiconductor device size shrinks without a concomitant increase of numerical aperture (NA) and refractive index of the immersion fluid, printing 22-nm-technology devices presents challenges in resolution. Therefore, aggressive integration of a resolution enhancement technique (RET), design for manufacturability (DFM), and layerspecific lithographic process development are strongly required in 22-nm-technology lithography. We show patterning of an active layer of a 22-nm-node planar logic transistor device, and discuss achievements and challenges. Key issues identified include printing tight pitches, isolated trench, and 2-D features while maintaining a large lithographic process window across the chip while scaling down the cell size. Utilizing NA=1.2, printing of the static random access memory (SRAM) of a cell size of 0.1 μm2 and other critical features across the chip with a process window are demonstrated. © 2010 Society of Photo-Optical Instrumentation Engineers.
S. Cohen, J.C. Liu, et al.
MRS Spring Meeting 1999
Elizabeth A. Sholler, Frederick M. Meyer, et al.
SPIE AeroSense 1997
Zelek S. Herman, Robert F. Kirchner, et al.
Inorganic Chemistry
Thomas H. Baum, Carl E. Larson, et al.
Journal of Organometallic Chemistry