22 nm technology node active layer patterning for planar transistor devices
- Ryoung-Han Kim
- Steven Holmes
- et al.
- 2009
- SPIE Advanced Lithography 2009
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4 results for Vito Dai
Overcoming the challenges of 22-nm node patterning through litho-design co-optimization
- Martin Burkharde
- J.C. Arnold
- et al.
- 2009
- SPIE Advanced Lithography 2009
32 NM Logic patterning options with immersion lithography
- K. Lai
- S. Burns
- et al.
- 2008
- SPIE Advanced Lithography 2008
22-nm-node technology active-layer patterning for planar transistor devices
- Ryoung-Han Kim
- Steven Holmes
- et al.
- 2010
- J. Micro/Nanolithogr. MEMS MOEMS