Sebastian Engelmann

Title

RSM, Quantum System Components Lead

Bio

Sebastian Engelmann received his Ph.D. in Materials Science at the University of Maryland, College Park in 2008. His main research activities in Prof. Gottlieb Oehrlein's group were improving the fundamental understanding of plasma-polymer interactions with main focus on 193nm PR resist materials interactions.

He then joined the Advanced Plasma Processing group at the IBM T.J. Watson Research Center in Yorktown Heights, N.Y, where he was developing plasma etch processes to support current and future device generations for exploratory CMOS device research and devices beyond the CMOS era. His main research activities are developing plasma processes that enable the integration of Trigate and Nanowire device geometries, novel materials (SiGe, III-V etc) or completely new technology apporaches (Photonics, MRAM, packaging etc.). Since 2015 he was also manager of the plasma processing group, looking at pioneering new uses of plasma etch technology in conventional and novel applications.

He recently joined the IBM Quantum organization to drive hardware component development for current and future quantum computing systems and is leading global efforts on developing supply chain and hardware ecosystems in this space.

Current and Prior Positions

IBM Quantum

System Components Lead

9/2021 - Present

Drive Quantum Systems Roadmap

IBM
Research Staff Member and Manager
10/2015 - 8/2021
Manage the advanced plasma processing group in Yorktown

IBM
Research Staff Member
9/2008 - Present
develop disruptive technologies

Publications

Sub-30 nm pitch line-space patterning of semiconductor and dielectric materials using directed self-assembly
- - Hsin-Yu Tsai
  - Hiroyuki Miyazoe
  - et al.
- 2012
- Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics
Improved frequency response in a SiGe npn device through improved dopant activation
- - Jim Adkisson
  - Marwan H. Khater
  - et al.
- 2012
- ECS Meeting 2012
Characterization and mechanism of He plasma pretreatment of nanoscale polymer masks for improved pattern transfer fidelity
- - Florian Weilnboeck
  - D. Metzler
  - et al.
- 2011
- Applied Physics Letters
Scaling of SOI FinFETs down to fin width of 4 nm for the 10nm technology node
- - Josephine Chang
  - Michael A. Guillorn
  - et al.
- 2011
- VLSI Technology 2011
A 0.021 μm² trigate SRAM cell with aggressively scaled gate and contact pitch
- - Michael A. Guillorn
  - Josephine Chang
  - et al.
- 2011
- VLSI Technology 2011
Systematic studies on reactive ion etch-induced deformations of organic underlayers
- - Martin Glodde
  - Sebastian Engelmann
  - et al.
- 2011
- SPIE Advanced Lithography 2011
Metallization opportunities and challenges for future back-end-of-the-line technology
- - Cyril Cabral Jr.
  - Benjamin Fletcher
  - et al.
- 2010
- ADMETA 2010
Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm
- - Sarunya Bangsaruntip
  - A. Majumdar
  - et al.
- 2010
- VLSI Technology 2010
Gate-all-around silicon nanowire MOSFETs and circuits
- - Jeffrey W. Sleight
  - Sarunya Bangsaruntip
  - et al.
- 2010
- DRC 2010
Reflectance and substrate currents of dielectric layers under vacuum ultraviolet irradiation
- - H. Sinha
  - D.B. Straight
  - et al.
- 2010
- JVSTA

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Patents

- 05 Aug 2024
- US
- 12057322
Methods For Etching Metal Films Using Plasma Processing
- 07 Mar 2022
- US
- 11270893
Layer-by-layer Etching Of Poly-granular Metal-based Materials For Semiconductor Structures
- 21 Feb 2022
- US
- 11258012
Oxygen-free Plasma Etching For Contact Etching Of Resistive Random Access Memory
- 24 May 2021
- US
- 11018225
Iii-v Extension By High Temperature Plasma Doping
- 11 May 2020
- US
- 10651286
High Selectivity Nitride Removal Process Based On Selective Polymer Deposition
- 06 Jan 2020
- US
- 10529633
Method Of Integrated Circuit (ic) Chip Fabrication
- 29 Jul 2019
- US
- 10366918
Self-aligned Trench Metal-alloying For Iii-v Nfets
- 17 Jun 2019
- US
- 10325998
High Selectivity Nitride Removal Process Based On Selective Polymer Deposition
- 27 May 2019
- US
- 10305029
Image Reversal Process For Tight Pitch Pillar Arrays
- 27 May 2019
- US
- 10304692
Method Of Forming Field Effect Transistor (fet) Circuits, And Forming Integrated Circuit (ic) Chips With The Fet Circuits

Top collaborators

Sebastian Engelmann

Title

Bio

Publications

Sub-30 nm pitch line-space patterning of semiconductor and dielectric materials using directed self-assembly

Improved frequency response in a SiGe npn device through improved dopant activation

Characterization and mechanism of He plasma pretreatment of nanoscale polymer masks for improved pattern transfer fidelity

Scaling of SOI FinFETs down to fin width of 4 nm for the 10nm technology node

A 0.021 μm² trigate SRAM cell with aggressively scaled gate and contact pitch

Systematic studies on reactive ion etch-induced deformations of organic underlayers

Metallization opportunities and challenges for future back-end-of-the-line technology

Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm

Gate-all-around silicon nanowire MOSFETs and circuits

Reflectance and substrate currents of dielectric layers under vacuum ultraviolet irradiation

Patents

Methods For Etching Metal Films Using Plasma Processing

Layer-by-layer Etching Of Poly-granular Metal-based Materials For Semiconductor Structures

Oxygen-free Plasma Etching For Contact Etching Of Resistive Random Access Memory

Iii-v Extension By High Temperature Plasma Doping

High Selectivity Nitride Removal Process Based On Selective Polymer Deposition

Method Of Integrated Circuit (ic) Chip Fabrication

Self-aligned Trench Metal-alloying For Iii-v Nfets

High Selectivity Nitride Removal Process Based On Selective Polymer Deposition

Image Reversal Process For Tight Pitch Pillar Arrays

Method Of Forming Field Effect Transistor (fet) Circuits, And Forming Integrated Circuit (ic) Chips With The Fet Circuits

Top collaborators

Nathan Marchack

William Green

Dominik Metzler

Vijay Narayanan