Vertical 2T-nC FeRAM Demonstration: BEOL Read Transistor for 4F2 Memory Strings and Two-Terminal Selector Design for Polarization Disturb Mitigation
- Shan Deng
- John Howe
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paper
Publications
13 results at VLSI Technology and Circuits 2025
NanoStack Transistor Architecture for CMOS 7A Node and Beyond
- S. Reboh
- C. Zhang
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paperA 6+ Ghz 128Kb Multi-Port L1 Cache Using Ground Rule Clean 10T Bitcells in 5Nm Technology
- Rajiv Joshi
- John Davis
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paperA 5.6-100K, 128ppm/K Cryo-CMOS Current Reference
- Subhajit Ray
- David Frank
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paperCompressive Diffusion Break Stressor for Gate-All-Around Nanosheet pFET Transistor Performance Improvement
- S. Hung
- S. Mochizuki
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paperScaled-Footprint Ultra-Low Power Cryogenic InGaAs/InP HEMTs with Record-High Combination of Low-Noise and High-Frequency Performance
- Alberto Ferraris
- Eunjung Cha
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paperNovel Advanced Low-k Dielectric for 2 nm and Beyond Cu and Post Cu Dual Damascene BEOL Interconnect Technologies
- S. Nguyen
- H. Huang
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paperBackside Routing Enablement Considerations For Advanced Node GAA Devices
- Kumar Subramani
- Rwik Sengupta
- et al.
- 2025
- VLSI Technology and Circuits 2025
Invited talkTile Efficiency is not System Efficiency – CIM architecture studies of LLMs and other large DNNs
- Pritish Narayanan
- 2025
- VLSI Technology and Circuits 2025
Workshop paperHeterogeneous neural processing units leveraging analog in-memory computing for edge AI
- 2025
- VLSI Technology and Circuits 2025
Workshop paper