A 7-nm Four-Core Mixed-Precision AI Chip with 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling
- Sae Kyu Lee
- Ankur Agrawal
- et al.
- 2021
- IEEE JSSC
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16 results for Kyu-Hyoun Kim
Vref optimization in DDR4 RDIMMs for improved timing margins
- Saravanan Sethuraman
- Anil Lingambudi
- et al.
- 2014
- EDAPS 2014
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC
- Monodeep Kar
- Joel Silberman
- et al.
- 2024
- IEEE Journal of Solid-State Circuits
Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem
- Saravanan Sethuraman
- Venkata Kalyan Tavva
- et al.
- 2020
- IEEE TCADIS
An 8 Gb/s/pin 9.6 ns row-cycle 288 Mb deca-data rate SDRAM with an I/O error detection scheme
- Kyu-Hyoun Kim
- Hoe-Ju Chung
- et al.
- 2007
- IEEE Journal of Solid-State Circuits
A second order mixed-mode charge pump scheme for low phase/duty error and low power consumption
- Kyu-Hyoun Kim
- In-Young Chung
- 2007
- IEICE Transactions on Electronics