Vref optimization in DDR4 RDIMMs for improved timing margins

Abstract

JEDEC DDR4 SDRAM adopted the internal Data (DQ) reference voltage (VREFDQ) generation scheme as opposed to DDR3 SDRAM where VREF was generated by an external device that produced fixed (constant) voltage irrespective of the loading on the device, power supply variations, temperature changes, and the passage of time. With the introduction of Per DRAM Addressability (PDA) in DDR4 memory and the internal VREF combined, discussed in this paper is a novel approach to determine the best VREF settings for a given topology. We will use memory controller built-in-self-test (MCBIST) to get a stressed pattern in place of simple Multi Purpose Register (MPR) data pattern and will be exercised as part of post DRAM training. Data pattern complexity, total training time and accuracy of training are investigated and optimized. Initial training of the DRAM is done with the initial VREF calculated based on driver strength and On Die Termination (ODT) condition. Complexities of different VREF settings are applied on multiple ranks in the same DIMM using the PDA to maximize timing margin and power efficiency. Per-DRAM VREF training has been also performed using PDA to study tradeoff between timing margin and total training time. Our results show significant benefits with respect to PDA vs rank basis Vref training.