Improving the energy/power constraint for technology optimization
- David J. Frank
- Leland Chang
- et al.
- 2011
- IEDM 2011
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59 results for Leland Chang
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation
- Gary S. Ditlow
- Robert K. Montoye
- et al.
- 2011
- ISSCC 2011
A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS
- Masood Qazi
- Kevin Stawiasz
- et al.
- 2010
- ISSCC 2010
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
- H. Kawasaki
- V.S. Basker
- et al.
- 2009
- IEDM 2009
A non-iterative compact model for carbon nanotube FETs incorporating source exhaustion effects
- Lan Wei
- David J. Frank
- et al.
- 2009
- IEDM 2009
Demonstration of highly scaled FinFET SRAM cells with high-Κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond
- H. Kawasaki
- M. Khater
- et al.
- 2008
- IEDM 2008
Aggressively scaled (0.143 μm 2) 6T-SRAM cell for the 32 nm node and beyond
- D. Fried
- J. Hergenrother
- et al.
- 2004
- IEDM 2004
Highlights of the isscc 2013 processors and high performance digital sessions
- Timothy Fischer
- Byeong-Gyu Nam
- et al.
- 2014
- IEEE JSSC
A 7-nm Four-Core Mixed-Precision AI Chip with 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling
- Sae Kyu Lee
- Ankur Agrawal
- et al.
- 2021
- IEEE JSSC
A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering
- Suyoung Bang
- Jae-Sun Seo
- et al.
- 2016
- IEEE JSSC