A 1.8-pJ/bit 16x16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- CICC 2015
Publications
Date
Featured collections
Popular topics
26 results for Ankur Agrawal
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2014
- CICC 2014
Area efficient phase calibration of a 1.6 GHz multiphase DLL
- Ankur Agrawal
- Pavan Kumar Hanumolu
- et al.
- 2011
- CICC 2011
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC
- Monodeep Kar
- Joel Silberman
- et al.
- 2024
- IEEE Journal of Solid-State Circuits
Efficient AI System Design with Cross-Layer Approximate Computing
- Swagath Venkataramani
- Xiao Sun
- et al.
- 2020
- Proceedings of the IEEE
A Scalable Multi-TeraOPS Core for AI Training and Inference
- Sunil Shukla
- Bruce Fleischer
- et al.
- 2018
- IEEE SSC-L