High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
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5 results for E. Engbrecht
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Optimization of Cu damascene electrodeposition process in ULSI for yield and reliability improvement
- Ingrid Shao
- T. Cheng
- et al.
- 2013
- ECS Transactions
Evaluation of barrier CMP slurries and characterization of ULK material properties shifts due to CMP
- Wei-Tsu Tseng
- Dimitri Kioussis
- et al.
- 2008
- ECS Meeting 2008
Evaluation of Cu CMP barrier slurries for Ultra Low-k dielectric film (k~2.4) for 45nm technology
- Feng Zhao
- Laertis Economikos
- et al.
- 2007
- ICPT 2007