Overcoming the challenges of 22-nm node patterning through litho-design co-optimization
- Martin Burkharde
- J.C. Arnold
- et al.
- 2009
- SPIE Advanced Lithography 2009
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6 results for Zachary Baum
32 NM Logic patterning options with immersion lithography
- K. Lai
- S. Burns
- et al.
- 2008
- SPIE Advanced Lithography 2008
Paving the way to a full chip gate level double patterning application
- Henning Haffner
- Jason Meiring
- et al.
- 2007
- SPIE Photomask Technology + EUV Lithography 2007
Mastering double exposure process window aware OPC by means of virtual targets
- Henning Haffner
- Zachary Baum
- et al.
- 2006
- SPIE Photomask Technology 2006
High-performance circuit design for the RET-enabled 65nm technology node
- Lars Liebmann
- Arnold Barish
- et al.
- 2004
- AMM 2004
Application of E-beam hot spot inspection for early detection of systematic patterning problems to a FinFET technology
- Deborah A. Ryan
- Oliver D. Patterson
- et al.
- 2015
- J. Micro/Nanolithogr. MEMS MOEMS