CLEAR: Crosslayer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores
- Eric Cheng
- Shahrzad Mirkhani
- et al.
- 2016
- DAC 2016
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32 results for Chen-Yong Cher
BRAVO: Balanced Reliability-Aware Voltage Optimization
- Karthik Swaminathan
- Nandhini Chandramoorthy
- et al.
- 2017
- HPCA 2017
Understanding soft errors in uncore components
- Hyungmin Cho
- Chen-Yong Cher
- et al.
- 2015
- DAC 2015
Quantitative evaluation of soft error injection techniques for robust system dsesign
- Hyungmin Cho
- Shahrzad Mirkhani
- et al.
- 2013
- DAC 2013
A wire-speed power™ processor: 2.3GHz 45nm SOI with 16 cores and 64 threads
- Charles Johnson
- David H. Allen
- et al.
- 2010
- ISSCC 2010
Software-controlled priority characterization of POWERS processor
- Carlos Boneti
- Francisco J. Cazorla
- et al.
- 2008
- ISCA 2008
An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget
- Canturk Isci
- Alper Buyuktosunoglu
- et al.
- 2006
- MICRO 2006
SMT malleability in IBM POWER5 and POWER6 processors
- Alessandro Morari
- Carlos Boneti
- et al.
- 2013
- IEEE TC
Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency
- William J. Song
- Alper Buyuktosunoglu
- et al.
- 2016
- ISLPED 2016
Understanding Error Propagation in GPGPU Applications
- Guanpeng Li
- Karthik Pattabiraman
- et al.
- 2016
- SC 2016