Topological semimetals for scaled back-end-of-line interconnect beyond Cu
- Ching-Tzu Chen
- Utkarsh Bajpai
- et al.
- 2020
- IEDM 2020
Publications
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62 results for Nick Lanzillo
Fully subtractive Ru Topvia interconnects with minimum 9 nm-space airgap for RC performance and reliability enhancement as post-Cu interconnects
- Koichi Motoyama
- Jaemyung Choi
- et al.
- 2024
- IEDM 2024
Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
- Chen Zhang
- Seungmin Song
- et al.
- 2024
- IEDM 2024
Backside power distribution for nanosheet technologies beyond 2nm
- Ruilong Xie
- Wonhyuk Hong
- et al.
- 2024
- VLSI Technology and Circuits 2024
Methodology Development to Benchmark Power Delivery Designs in Advanced Technology Nodes
- Nicholas A. Lanzillo
- A. Chu
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling
- C. J. Penny
- Koichi Motoyama
- et al.
- 2022
- IEDM 2022
Advanced BEOL Materials, Processes, and Integration to Reduce Line Resistance of Damascene Cu, Co, and Subtractive Ru Interconnects
- Takeshi Nogami
- Oleg Gluschenkov
- et al.
- 2022
- VLSI Technology and Circuits 2022
Resistivity scaling in topological semimetal CoSi
- Hsin Lin
- Shang-Wei Lien
- et al.
- 2022
- APS March Meeting 2022
Electromigration and Line R of Graphene Capped Cu Dual Damascene Interconnect
- T. Nogami
- S. Nguyen
- et al.
- 2021
- IEDM 2021
Interconnect scaling challenges, and opportunities to enable system-level performance beyond 30 nm pitch
- Griselda Bonilla
- Nicholas A. Lanzillo
- et al.
- 2020
- IEDM 2020