Design methodology for a 1.0 GHz microprocessor
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 1998
- ICCD 1998
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38 results for Peter Hofstee
High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor
- D. Heidel
- S. Dhong
- et al.
- 1998
- VTS 1998
690ps read-access latency register file for a GHz integer microprocessor
- O. Takahashi
- Joel Silberman
- et al.
- 1998
- ICCD 1998
Circuits and microarchitecture for Gigahertz VLSI designs
- K. Nowka
- H.P. Hofstee
- 1997
- ARVLSID 1997
Optimizing performance of GATK workflows using Apache Arrow In-Memory data framework
- Tanveer Ahmad
- Nauman Ahmed
- et al.
- 2020
- BMC Genomics
A hardware compilation framework for text analytics queries
- Raphael Polig
- Kubilay Atasu
- et al.
- 2018
- JPDC
PATer: A hardware prefetching automatic tuner on IBM POWER8 processor
- Minghua Li
- Guancheng Chen
- et al.
- 2016
- IEEE Computer Architecture Letters
Feature detection for image analytics via FPGA acceleration
- H.-Y. Chang
- Iris Hui Ru Jiang
- et al.
- 2015
- IBM J. Res. Dev
Giving Text Analytics a Boost
- Raphael Polig
- Kubilay Atasu
- et al.
- 2014
- IEEE Micro
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI
- Brian Flachs
- Shigehiro Asano
- et al.
- 2007
- IBM J. Res. Dev