'Timing Closure by Design,' a high frequency microprocessor design methodology
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 2000
- DAC 2000
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10 results for Brian Flachs
A 1GHz single-issue 64b powerPC processor
- H.P. Hofstee
- Naoaki Aoki
- et al.
- 2000
- ISSCC 2000
Distributed on-chip power supply noise characterization of the cell broadband engine™
- Yaping Zhou
- Paul M. Harvey
- et al.
- 2007
- IEEE Topical Meeting EPEPS 2007
The circuits and physical design of the synergistic processor element of a CELL processor
- O. Takahashi
- R. Cook
- et al.
- 2005
- VLSI Circuits 2005
The circuit design of the synergistic processor element of a CELL processor
- O. Takahashi
- R. Cook
- et al.
- 2005
- ICCAD 2005
A resonant global clock distribution for the cell broadband engine processor
- Steven C. Chan
- Phillip J. Restle
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI
- Brian Flachs
- Shigehiro Asano
- et al.
- 2007
- IBM J. Res. Dev
Synergistic processing in cell's multicore architecture
- Michael Gschwind
- H. Peter Hofstee
- et al.
- 2006
- IEEE Micro
Power-conscious design of the cell processor's synergistic processor element
- Osamu Takahashi
- Scott Cottier
- et al.
- 2005
- IEEE Micro
The hector distributed run-time environment
- Samuel H. Russ
- Jonathan Robinson
- et al.
- 1998
- IEEE TPDS